1. Field of the Invention
The present invention relates to analog-to-digital (A-D) converters, and it particularly relates to a technology by which to improve the performance of pipeline type A-D converters.
2. Description of the Related Art
In the conventional practice, the sample-and-hold circuits and amplifier circuits have been utilized to constitute the multi-stage pipeline type analog-to-digital converters (hereinafter referred to as xe2x80x9cA-D convertersxe2x80x9d) (see the following Related Art List for reference). The ranges of voltages that can be outputted are determined in advance according to the respective characteristics of circuits.
Related Art List
(1) Japanese Patent Application Laid-Open No. Hei09-275342, pages 9-16, FIG. 1
(2) Japanese Patent Application Laid-Open No. Hei09-69776, pages 4-6, FIG. 1
The output voltage of the above-mentioned circuit is theoretically proportional to the input voltage thereof. However, beyond or outside an effective output range which is a characteristic to be determined by the circuit, the resulting output may not necessarily be proportional to the input thereof. Hence, depending on the input voltage value, there has always been a possibility that the conversion accuracy drops with an incorrect value conveyed to a next stage.
On the other hand, it has been an important design challenge to achieve a lower-voltage design for an A-D converter as a whole. Yet designing a circuit with a wider output range therefore goes counter to it. Besides, as equipment of lower-voltage design increase, there will be greater need for circuits with narrower output range.
The present invention has been made in view of the foregoing circumstances and an object thereof is to raise the conversion accuracy of an A-D converter.
A preferred embodiment according to the present invention relates to a signal conversion method. This method includes: determining the range of an input signal; setting a level of a reference signal according to the determining so that the input signal falls within a satisfactory range in terms of conversion performance thereof; holding a signal value obtained as a result of adjustment to the input signal using the reference signal; converting the input signal to a target signal in parallel with the holding; and offsetting temporary variation caused in the input signal held in the holding.
The determining may determine whether a voltage value of the input signal is positive or negative or whether the input signal falls within a predetermine range or not. The xe2x80x9cconversion performancexe2x80x9d may be capability or capacity such as accuracy and efficiency at the time the input signal is converted into a desired format. The xe2x80x9csatisfactory rangexe2x80x9d is the range, for example, in which an ideal value or expected value is achieved in the input-output characteristics of elements constituting a conversion circuit. The xe2x80x9creference signalxe2x80x9d is a signal set based on a reference voltage and, for example, the xe2x80x9creference signalxe2x80x9d may be referred to by a circuit in which a value of the input signal is acquired and held temporarily when the above conversion is processed.
The reference signal is set to different values according to the range of the input signal. When the reference signal is set to a value other than 0V, the value held by the circuit is temporarily varied and does not indicate a proper value. On the other hand, the value held by the circuit belongs to a range that keeps the conversion performance satisfactory. The temporary variation is cancelled out or offset by making another adjustment during the conversion processing. By implementing the above method, the input signal can be converted into a target signal while the conversion performance is kept in a desirable state. Since the voltage value of the input signal does not exceed or become outside a predetermined range, the conversion under low voltage is possible, thus reducing the power consumption.
Another preferred embodiment according to the present invention relates to a signal conversion circuit. This circuit includes: a first adjustment unit which sets a level of a reference signal according to a range of an input signal so that values of the input signal fall within a satisfactory range in terms of conversion performance thereof; a second adjustment unit which offsets temporary variation which is caused in the input signal and by operation of the reference signal thereon, during converting the input signal into a target signal.
The first adjustment unit may include a sample-and-hold circuit which samples a signal based on a reference signal and holds this, or an amplifier circuit which amplifies a signal based on the reference signal. The outputs of these circuits may vary, due to the level-adjusted reference signal operated thereon, in a manner such that the outputs thereof fall within a fixed range. Thereby, the output values are kept proportional to the input values. As methods of canceling out or offsetting the variation by the second adjustment unit, there is, for example, a method where the value held at the sample-and-hold circuit is modified and then adjusted.
By implementing the above circuit, the input signal can be converted into a target signal while the conversion performance is kept in a desirable state. Since the voltage value of the input signal does not exceed or become outside a fixed range, the conversion under low voltage is possible, thus reducing the power consumption.
Still another preferred embodiment according to the present invention relates to an analog-to-digital conversion circuit. This circuit includes: a first adjustment unit which sets a level of a reference signal according to a range of an input analog voltage so that values of the input analog voltage fall within a satisfactory range in terms of conversion performance thereof; an analog-to-digital (A-D) conversion unit which converts the values of the input analog voltage into digital values; and a second adjustment unit which offsets temporary variation which is caused in the values of the input analog voltage and as a result of the reference signal operated thereon during A-D conversion.
The A-D conversion unit is comprised of a plurality of comparators, encoders and so forth so as to convert input analog voltage values into digital values represented by a predetermined bit number. Thus, this A-D conversion unit can be interpreted or thought of as an analog-to-digital (A-D) converter in a narrow sense. There may be provided a plural stages of such A-D converter units so as to realize a pipeline structure which generates one or more bit digital value(s), based on the input analog voltage, gradually from a high-order bit at each of the stages thereof. In such a case, the allocation as to how many bits are to be generated for each stage can be arbitrarily set based on a design concept. The first adjustment unit and the second adjustment unit may be provided at any of the stages.
The first adjustment unit may include at lease one comparator which determines the range of the input analog voltage and a sample-and-hold unit which holds a value obtained in a manner such that temporary variation is added to the value of the input analog voltage based on the thus set reference signal so that the values of the input analog voltage fall within the satisfactory range. The second adjustment unit may include: a digital-to-analog (D-A) conversion unit which converts the digital value into an analog value and makes an adjustment to offset the temporary variation thereof; and a differential amplifier circuit which subtracts the thus converted analog value from the analog voltage value held at the sample-and-hold unit and amplifies the thus obtained signal.
If there is unintentional error in the value held by the sample-and-hold circuit, the overall accuracy of the A-D conversion will deteriorate. Thus, artificial variation is, inadvance, added to the input voltage which may cause the error to the output of the sample-and-hold circuit, on the condition that the added artificial variation is offset at a later stage. As a result thereof, the overall error is reduced. Variation same as the added variation is reflected on the output value of the D-A conversion circuit so as to be offset.
By implementing the above circuit, the A-D conversion performance is kept desirable and it is possible to perform the conversion at lower voltage, thus further reducing the power consumption. Moreover, circuits used for the adjustment can be realized by an internal design including a sample-and-hold circuit and a D-A conversion circuit, so that the overall necessary structure can be minimized.
Still another preferred embodiment according to the present invention relates also to an analog-to-digital conversion circuit. This circuit is a signal conversion circuit for converting analog signals into digital signals, and the circuit includes: analog-to-digital (A-D) conversion unit which acquires an input analog voltage value and then converts the acquired input analog voltage value into a digital value of a predetermined bit number; and a sample-and-hold unit which acquires and holds a value adjusted so that input analog voltage to be acquired by the A-D conversion unit falls within a satisfactory range in terms of conversion performance thereof.
This circuit according to this preferred embodiment shares the common points with other preferred embodiments in that the adjustment is made in such a manner as to ideally keep the input-output relation of the sample-and-hold circuit. On the other hand, the point especially characteristic to this embodiment and different from the other embodiments is that the values to be converted by the A-D conversion unit differ from those to be held by the sample-and-hold circuit. Namely, the input analog value is inputted, intact, to the A-D conversion unit and an adjusted value of the input analog value is inputted to the sample-and-hold unit. Thus, the A-D conversion unit converts analog values which are available before the sample-and-hold unit holds. Moreover, when the digital output of the A-D conversion unit is converted again into analog values, the similar adjustment to the sample-and-hold unit is made thereto, so that overall conversion accuracy is kept at the desired level.
The value to be inputted to the sample-and-hold unit may be a value obtained by again converting the output from the A-D conversion unit into an analog value and subtracting the thus converted analog value from the original analog value. In such a case, the voltage value becomes small to a certain degree before being inputted to the sample-and-hold unit, so that the conversion performance is likely to fall within a desired range. By implementing these structures, the A-D conversion performance is kept desirable and it is possible to perform the conversion at lower voltage, thus further reducing the power consumption.
It is to be noted that any arbitrary combination of the above-described structural components and expressions changed between a method, an apparatus, a system and so forth are all effective as and encompassed by the present embodiments.
Moreover, this summary of the invention does not necessarily describe all necessary features so that the invention may also be sub-combination of these described features.